Semiconductor memory devices are memory devices that are made of semiconductors materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). In general, semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.
Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM). Nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM). Flash memory devices are categorized as two types, i.e., NOR type and NAND type.
In the early stage, a flash memory device can store two states (1 bit) in a single memory cell. With the advance in technology, two bits or more can be stored in a single memory cell. That is, a multi-media cell (MLC) technology has been developed to store more data in a limited cell. However, with the shrinkage of processes, sizes of memory cells are reduced and coupling between the memory cells is increased, which can deteriorate dispersion characteristics of the memory cells and increase non-uniformity of the memory cells. In addition, if program/erase operations are repeated, dispersion characteristics of the memory cells are further degraded and may limit lifetime of a flash memory.
SUMMARY
Integrated circuit memory systems according to embodiments of the invention include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells, in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle.
According to some embodiments of the invention, the memory controller is configured to apply first signals to the nonvolatile memory device that cause the nonvolatile memory device to read first data from a first row of memory cells in the array of nonvolatile memory cells and perform error checking and correction (ECC) operations on the first data. The memory controller may also be configured to apply second signals to the nonvolatile memory device that cause the nonvolatile memory device to reread the first data from the first row of memory cells in the array of nonvolatile memory cells, in response to detecting an excessive number of errors in the first data during the error detection/correction operations. These second signals are configured to increase an accuracy of the rereading of the first data from the first row of memory cells relative to the first signals. For example, the second signals may be applied to the nonvolatile memory device to cause a rereading of the first data and also cause the reading of “coupling” data from cells that are immediately adjacent the first row of memory cells. This coupling data may then be utilized to assess the reliability of the first data during the error checking and correction operations.
According to still further embodiments of the invention, a method of operating a nonvolatile memory device is provided, which includes reading first data from a first row of nonvolatile memory cells in a nonvolatile memory array and performing a first error checking operation on the first data to detect a presence of at least one error therein. Additional steps are also performed to read second data from a plurality of nonvolatile memory cells in a second row of the nonvolatile memory array, which is immediately adjacent the first row. This step of reading the second data is performed in response to detecting errors in the first data when the first error checking operation is performed. Following the reading of the second data, a second error checking operation is performed on the first data. This second error checking operation uses the second data to influence how the second error checking operation interprets the first data.
These methods may also include reading third data from a third row of nonvolatile memory cells in the nonvolatile memory array and performing a third error checking operation on the third data to detect a presence of any error therein. Any errors in the third data may then be corrected using an error correction algorithm. The reading of the second data may also be performed in response to detecting errors in the first data that cannot be corrected using the error correction algorithm.